Principles of verifiable RTL design :a functional coding style supporting verification processes in Verilog

• 作者: Bening, Lionel,
• 其他作者: Foster, Harry,
• 出版: Norwell, Mass. : Kluwer Academic Publishers ©2000.
• 稽核項: 1 online resource (xvii, 253) :illustrations.
• 標題: Electronic books. , Machine Theory. , Verilog (Computer hardware description language) , Circuits intégrés à très grande échelle , Integrated circuits Very large scale integration -- Computer-aided design. , Computer Engineering. , COMPUTERS , COMPUTERS Hardware -- General. , Ordinateurs Conception assistée par ordinateur. , HardwareGeneral. , COMPUTERS Machine Theory. , Very large scale integrationComputer-aided design. , Verilog (Langage de description de matériel informatique) , Ordinateurs , Electronic digital computers , COMPUTERS Computer Engineering. , Conception assistée par ordinateur. , Computer-aided design. , Circuits intégrés à très grande échelle Conception assistée par ordinateur. , Electronic digital computers Computer-aided design. , Integrated circuits
• ISBN: 0306470160 , 9780306470165
• ISBN: 0792377885 , 9780792377887
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• 附註: Includes bibliographical references (pages 231-238) and index. Cover -- Table of Contents -- PREFACE -- 1 Introduction -- 1.1 Register Transfer Level -- 1.2 Assumptions -- 1.3 Organization of This Book -- 2 The Verification Process -- 2.1 Specification Design Decomposition -- 2.2 Functional Test Strategies -- 2.3 Transformation Test Strategies. -- 2.4 Coverage -- 2.5 Event Monitors and Assertion Checkers -- 2.6 Summary -- 3 RTL Methodology Basics -- 3.1 Simple RTL Verifiable Subset -- 3.2 Object-Oriented Hardware Design -- 3.3 Linting -- 3.4 Summary -- 4 RTLLogic Simulation -- 4.1 Simulation History -- 4.2 Project Simulation Phases -- 4.3 Operation -- 4.4 Optimizations -- 4.5 Random Two-State Simulation Methods -- 4.6 Summary -- 5 RTL Formal Verification -- 5.1 Formal Verification Introduction -- 5.2 Finite State Machines -- 5.3 Formal Transformation Verification -- 5.4 Formal Functional Verification -- 5.5 Model Checking Methodology -- 5.6 Summary -- 6 Verifiable RTL Style -- 6.1 Design Content -- 6.2 Organization -- 6.3 Naming Conventions -- 6.4 Naming In Verilog Library Modules -- 6.5 Editing Practices -- 6.6 Summary -- 7 The Bad Stuff -- 7.1 In-line Storage Element Specification -- 7.2 RTL X State -- 7.3 Visits -- 7.4 Simulationvs. Synthesis Differences -- 7.5 EDA Tool Vendors -- 7.6 Design Team Discipline -- 7.7 Language Elements -- 7.8 Summary -- 8 Verifiable RTLTutorial -- 8.1 Module -- 8.2 Adding Behavior -- 8.3 Multi-bit Interconnect and Behavior -- 8.4 Expressions -- 8.5 Procedural Blocks -- 8.6 Testbench -- 8.7 Verilog Compilation -- 8.8 Summary -- 9 Principles of Verifiable RTL Design -- 9.1 Principles -- 9.2 Summary -- Bibliography -- A Comparing Verilog Construct Performance -- B Quick Reference.
• 摘要: Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog explains how you can write Verilog to describe chip designs at the RT-level in a manner that cooperates with verification processes. This cooperation can return an order of magnitude improvement in performance and capacity from tools such as simulation and equivalence checkers. It reduces the labor costs of coverage and formal model checking by facilitating communication between the design engineer and the verification engineer. It also orients the RTL style to provide more useful results from the overall verification process. The intended audience for Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog is engineers and students who need an introduction to various design verification processes and a supporting functional Verilog RTL coding style. A second intended audience is engineers who have been through introductory training in Verilog and now want to develop good RTL writing practices for verification. A third audience is Verilog language instructors who are using a general text on Verilog as the course textbook but want to enrich their lectures with an emphasis on verification. A fourth audience is engineers with substantial Verilog experience who want to improve their Verilog practice to work better with RTL Verilog verification tools. A fifth audience is design consultants searching for proven verification-centric methodologies. A sixth audience is EDA verification tool implementers who want some suggestions about a minimal Verilog verification subset. Principles of Verifiable RTL Design: A Functional Coding Style Supporting Verification Processes in Verilog is based on the reality that comes from actual large-scale product design process and tool experience.
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