附註:Includes index.
COVER -- TABLE OF CONTENTS -- LIST OF FIGURES -- LIST OF EXAMPLES -- LIST OF TABLES -- 1 INTRODUCTION -- Framing Verilog Concepts -- Where To Get More Information -- 2 INTRODUCTION TO THE VERILOG LANGUAGE -- Identifiers -- White Space -- Comments -- Numbers -- Text Macros -- Modules -- Semicolons -- Value Set -- Strengths -- Numbers, Values, and Unknowns -- 3 STRUCTURAL MODELING -- Primitives -- Ports -- Instances -- Hierarchy -- Hierarchical Names -- 4 BEHAVIORAL MODELING -- Starting Places for Places for Blocks of Behavioral Code -- System Tasks for Printing Out Results -- Data Objects in Verilog -- Procedural Assignments -- Ports and Registers -- 5 OPERATORS -- Binary Operators -- Unary Operators -- Reduction Operators -- Ternary Operator -- Equality Operators -- Concatenations -- Logical versus Bit-wise Operations -- Operations That Are Not Legal on Reals -- Working with Strings -- Combining Operators -- Sizing Expressions -- Signed Operations -- Signed Constants -- 6 WORKING WITH BEHAVIORAL MODELING -- Continuous Assignment -- Event Control -- The if Statement -- The case Statement -- Loops -- Procedural Continuous Assignments -- tasks -- functions -- A Reminder about Ports and Registers -- Modeling with inout Ports -- Named Blocks -- The disable Statement -- When is a Simulation Done? -- 7 USER-DEFINED PRIMITIVES -- Combinatorial UDPs -- Sequential UDPs -- UDP Instances -- The Final Details -- 8 PARAMETERIZED MODULES -- n-Bit Mux -- n-Bit Adder -- n By m Mux -- n By m Ram -- Using Parameterized Modules -- 9 STATE MACHINES -- State Machine Types -- State Machine Modeling Style -- State Encoding Methods -- Default Conditions -- Implicit State Machines -- Registered and Unregistered Outputs -- Factors in Choosing a State Machine Modeling Style -- 10 MODELING TIPS -- Modeling Combinatorial Logic -- Modeling Sequential Logic -- Modeling Asynchronous Circuits -- Special-Purpose Models -- Multiplier Examples -- A Proven, Successful Approach to Modeling -- 11 MODEL
摘要:From a review of the Second Edition 'If you are new to the field and want to know what "all this Verilog stuff is about," you've found the golden goose. The text here is straight forward, complete, and example rich -mega-multi-kudos to the author James Lee. Though not as detailed as the Verilog reference guides from Cadence, it likewise doesn't suffer from the excessive abstractness those make you wade through. This is a quick and easy read, and will serve as a desktop reference for as long as Verilog lives. Best testimonial: I'm buying my fourth and fifth copies tonight (I've loaned out/lost two of my others).' Zach Coombes, AMD.
