附註:Includes bibliographical references and index.
Cover -- Table of Contents -- Dedication -- Acknowledgements -- Preface -- Chapter 1 INTRODUCTION -- 1.1 A LITTLE HISTORICAL STORY -- 1.2 ESD FAILURE ... AN IC RELIABILITY PROBLEM -- 1.3 ON-CHIP ESD PROTECTION -- GENERAL REMEDY -- 1.4 CHALLENGES IN ESD PROTECTION DESIGN -- 1.5 SCOPE OF THIS BOOK -- REFERENCES -- Chapter 2 ESD TEST MODELS -- 2.1 NATURE OF ESD PHEMONEMA -- 2.2 HBM MODEL -- 2.3 MM MODEL -- 2.4 CDM MODEL -- 2.5 TLP MODEL -- 2.6 OTHER MODELS -- 2.7 ESD ZAPPING TESTS -- 2.8 SUMMARY -- REFERENCES -- Chapter 3 ESD PROTECTION DEVICE SOLUTIONS -- 3.1 ON-CHIP ESD PROTECTION MECHANISMS -- 3.2 DIODE AS ESD PROTECTION ELEMENT -- 3.3 BJT AS ESD PROTECTION ELEMENT -- 3.4 MOSFET AS ESD PROTECTION ELEMENT -- 3.5 SCR AS ESD PROTECTION ELEMENT -- 3.6 SUMMARY -- REFERENCES -- Chapter 4 ESD PROTECTION CIRCUIT SOLUTIONS -- 4.1 INPUT ESD PROTECTION SCHEMES -- 4.2 OUTPUT ESD PROTECTION SCHEMES -- 4.3 POWER CLAMPS -- 4.4 SUMMARY -- REFERENCES -- Chapter 5 ADVANCED ESD PROTECTION -- 5.1 ESD PROTECTION FOR MIXED-SIGNAL ICs -- 5.2 ESD PROTECTION FOR RF ICs -- 5.3 LOW-PARASITIC MULTIPLE-MODE SOLUTIONS -- 5.4 WHOLE-CHIP ESD PROTECTION SCHEMES -- 5.5 NON-PORTABILITY IN ESD PROTECTION -- 5.6 SUMMARY -- REFERENCES -- Chapter 6 ESD FAILURE ANALYSIS AND MODELING -- 6.1 WHY ESD FAILURE ANALYSIS? -- 6.2 ESD FA TECHNIQUES -- 6.3 SOME ESD FAILURE SIGNATURES -- 6.4 ESD FA CORRELATION -- 6.5 LATENT ESD FAILURE -- 6.6 ESD FAILURE MODELING AND CRITERIA -- 6.7 SUMMARY -- REFERENCES -- Chapter 7 LAYOUT AND TECHNOLOGY INFLUENCES ON ESD PROTECTION CIRCUIT DESIGN -- 7.1 LAYOUT vs. ESD PROTECTION -- 7.2 REGULAR LAYOUT FOR ESD PROTECTION -- 7.3 SPECIAL LAYOUT FOR ESD PROTECTION -- 7.4 ADVANCED LAYOUT DESIGN CONCEPTS -- 7.5 TECHNOLOGY SCALING vs. ESD PROTECTION -- 7.6 NEW TECHNOLOGY vs. ESD PROTECTION -- 7.7 ESD PROTECTION FOR SOI AND SiGe -- 7.8 ESD PROTECTION FOR NANO TECHNOLOGY -- 7.9 SUMMARY -- REFERENCES -- Chapter 8 ESD SIMULATION-DESIGN METHODOLOGIES -- 8.1 ESD PROTECTION DESIGN METHODS: TR
摘要:This comprehensive and insightful book discusses ESD protection circuit design problems from an IC designer's perspective. On-Chip ESD Protection for Integrated Circuits: An IC Design Perspective provides both fundamental and advanced materials needed by a circuit designer for designing ESD protection circuits, including: Testing models and standards adopted by U.S. Department of Defense, EIA/JEDEC, ESD Association, Automotive Electronics Council, International Electrotechnical Commission, etc. ESD failure analysis, protection devices, and protection of sub-circuits Whole-chip ESD protection and ESD-to-circuit interactions Advanced low-parasitic compact ESD protection structures for RF and mixed-signal IC's Mixed-mode ESD simulation-design methodologies for design prediction ESD-to-circuit interactions, and more! Many real world ESD protection circuit design examples are provided. The book can be used as a reference book for working IC designers and as a textbook for students in the IC design field.
