附註:Includes bibliographical references and index.
Machine generated contents note: List of Figures List of Tables Preface Contributors Acknowledgements Introduction 1.1 A connected world emerges 1.2 Wireless OFDM: the next technology wave 1.3 Wireless OFDM systems 1.4 Structure of the book Understanding the indoor environment 2.1 Introduction 2.2 Propagation losses 2.3 Multipath propagation 2.4 Time variant channels 2.5 Conclusions The OFDM Principle 3.1 The OFDM principle 3.2 The OFDM system model 3.3 What if the channel is time-variant? 3.4 OFDM receiver performance 3.5 Coding: an essential ingredient 3.6 Summary When people agree on OFDM 4.1 WLAN standards 4.2 HIPERLAN/2 4.3 Differences between HIPERLAN/2 and IEEE 802.1 la Beating the wireless channel 5.1 Introduction 5.2 Channel models and characteristics 5.3 One-Dimensional Channel Estimators 5.4 Two-Dimensional Channel estimators. Avoiding a tower of Babel 6.1 Introduction 6.2 Effects of out of sync transmission 6.3 Timing synchronisation 6.4 Frequency synchronisation Living with a real radio 7.1 Introduction 7.2 How the front-end impairs the OFDM modem 7.3 A system simulation tool 7.4 Analysis and simulation of the main front-end effects 7.5 Conclusions Putting it all together 8.1 Introduction 8.2 The basedband signal processing ASIC 8.3 The discrete system set-up 8.4 Learning from results.
Understanding the indoor environment -- The OFDM Principle -- When people agree on OFDM -- Beating the wireless channel -- Avoiding a tower of Babel -- Living with a real radio -- Putting it all together.
摘要:This book carefully details design tools and techniques for high-performance ASIC design. Using these techniques, the performance of ASIC designs can be improved by two to three times. Important topics include: Improving performance through microarchitecture; Timing-driven floorplanning; Controlling and exploiting clock skew; High performance latch-based design in an ASIC methodology; Automatically identifying and synthesizing complex logic gates; Automated cell sizing to increase performance and reduce power; Controlling process variation. These techniques are illustrated by designs running two to three times the speed of typical ASICs in the same process generation.
