附註:" ... an in-depth tutorial"--Cover.
Includes index.
Cover -- Table of Contents -- 1.0 VHDL OVERVIEW AND CONCEPTS -- 1.1 WHAT IS VHDL -- 1.2 LEVEL OF DESCRIPTIONS -- 1.3 METHODOLOGY AND CODING STYLE REQUIREMENTS -- 1.4 VHDL TYPES -- 1.5 VHDL OBJECT CLASSES -- 1.6 VHDL DESIGN UNITS -- 1.7 COMPILATION, ELABORATION, SIMULATION -- 2.0 BASIC LANGUAGE ELEMENTS -- 2.1 LEXICAL ELEMENTS -- 2.2 SYNTAX -- 2.3 TYPES AND SUBTYPES -- 2.4 FILE -- 2.5 ATTRIBUTES -- 2.6 ALIASES -- 3.0 CONTROL STRUCTURES -- 3.1 EXPRESSIONCLASSIFICATION -- 3.2 CONTROL STRUCTURES -- 4.0 DRIVERS -- 4.1 RESOLUTION FUNCTION -- 4.2 DRIVERS -- 4.3 PORTS -- 5.0 VHDL TIMING -- 5.1 SIGNAL ATTRIBUTES -- 5.2 THE "WAIT" STATEMENT -- 5.3 SIMULATION ENGINE -- 5.4 MODELING WITH DELTA TIME DELAYS -- 5.5 INERTIAL / TRANSPORT DELAY -- 6.0 ELEMENTS OF ENTITY/ARCHITECTURE -- 6.1 VHDL ENTITY -- 6.2 VHDL ARCHITECTURE -- 7.0 SUBPROGRAMS -- 7.1 SUBPROGRAM DEFINITION -- 7.2 SUBPROGRAM RULES AND GUIDELINES -- 7.3 SUBPROGRAM OVERLOADING -- 7.4 FUNCTIONS -- 7.5 RESOLUTION FUNCTION -- 7.6 OPERATOR OVERLOADING -- 7.7 CONCURRENT PROCEDURE -- 8.0 PACKAGES -- 8.1 PACKAGE -- 8.2 CONVERTING TYPED OBJECTS TO STRINGS -- 8.3 PACKAGE TEXTIO -- 8.4 DESIGN OF A LINEAR FEEDBACK SHIFT REGISTER (LFSR) -- 8.5 COMPILATION ORDER -- 9.0 USER DEFINED ATTRIBUTES, SPECIFICATIONS, AND CONFIGURATIONS -- 9.1 ATTRIBUTE DECLARATIONS -- 9.2 USER-DEFINED ATTRIBUTES -- 9.3 SPECIFICATIONS -- 9.4 CONFIGURATION SPECIFICATION -- 9.5 CONFIGURATION DECLARATION -- 10.0 DESIGN FOR SYNTHESIS -- 10.1 CONSTRUCTS FOR SYNTHESIS -- 10.2 REGISTER INFERENCE -- 10.3 COMBINATIONAL LOGIC INFERENCE -- 10.4 STATE MACHINE -- 10.5 RTL STATE MACHINE DESIGN STYLES -- 10.6 ARITHMETIC OPERATIONS -- 11.0 FUNCTIONAL MODELS AND TESTBENCHES -- 11.1 TESTBENCH MODELING -- 11.2 SCENARIO GENERATION SCHEMES -- 12.0 UART PROJECT -- 12.1 UARTARCHITECTURE -- 12.2 UART TESTBENCH -- 13.0 VITAL -- 13.1 VITAL -- 13.2 VITAL FEATURES -- 13.3 VITAL MODEL -- APPENDIX A VHDL'93 AND VHDL'81 SYNTAX SUMMARY -- APPENDIX B PACKAGE STANDARD -- APPENDIX C PACKAG
摘要:VHDL Coding Styles and Methodologies, Second Edition is a follow-up book to the first edition of the same book and to VHDL Answers to Frequently Asked Questions, first and second editions. This book was originally written as a teaching tool for a VHDL training course. The author began writing the book because he could not find a practical and easy-to-read book that gave in-depth coverage of both the language and coding methodologies. This new edition provides practical information on reusable software methodologies for the design of bus functional models for testbenches. It also provides guidelines in the use of VHDL for synthesis. Model Technology graciously included an evaluation version of ModelSim, a recognized industry standard VHDL/Verilog compiler and simulator that supports easy viewing of the models under analysis, along with many debug features. In addition, Synplicity is kindly making available an evaluation version of Synplify, a very efficient, user-friendly and easy-to-use FPGA synthesis tool. Synplify provides a user with both the RTL and gate-level views of the synthesized model, and a performance report of the design. Optimization mechanisms are provided in the tool. VHDL Coding Styles and Methodologies, Second Edition is intended for professional engineers as well as students. It is organized in thirteen chapters, each covering a separate aspect of the language, with complete examples. It provides a practical approach to learning VHDL. Combining methodologies and coding styles, along with VHDL rules, leads the reader in the right direction from the beginning.
