附註:Includes index.
Introduction -- Introduction to the Verilog Language -- Structural Modeling -- Starting Procedural Modeling -- System Tasks for Displaying Results -- Data Objects -- Procedural Assignments -- Operators -- Creating Combinatorial and Sequential Logic -- Procedural Flow Control -- Tasks and Functions -- Advanced Procedural Modeling -- User-Defined Primitives -- Parameterized Modules -- State Machines -- Modeling Tips -- Modeling Style Trade-Offs -- Test Benches and Test Management -- Model Organization -- Common Errors -- Debugging a Design -- Code Coverage -- Appendix A: Gate-Level Details.
Includes bibliographical references and index.
摘要:From a review of the Second Edition 'If you are new to the field and want to know what "all this Verilog stuff is about," you've found the golden goose. The text here is straight forward, complete, and example rich -mega-multi-kudos to the author James Lee. Though not as detailed as the Verilog reference guides from Cadence, it likewise doesn't suffer from the excessive abstractness those make you wade through. This is a quick and easy read, and will serve as a desktop reference for as long as Verilog lives. Best testimonial: I'm buying my fourth and fifth copies tonight (I've loaned out/lost two of my others).' Zach Coombes, AMD.
