Advanced verification techniques :a systemC based approach for successful tapeout
- 作者: Singh, Leena,
- 其他作者: Drucker, Leonard. , Khann, Neyaz.
- 出版: Boston : Kluwer Academic Publishers ©2004.
- 稽核項: 1 online resource (xviii, 376 pages) :illustrations.
- 標題: TECHNOLOGY & ENGINEERING , TECHNOLOGY & ENGINEERING Electronics -- Circuits -- General. , TECHNOLOGY & ENGINEERING Electronics -- Circuits -- Integrated. , Verification. , ElectronicsCircuitsIntegrated. , Integrated circuits Verification. , ElectronicsCircuitsGeneral. , Electronic books. , Integrated circuits
- ISBN: 140207672X , 9781402076725
- ISBN: 140207672X , 9781441954091 , 1441954090
- 試查全文@TNUA:
- 附註: Includes bibliographical references (pages 371-372) and index. Introduction -- Verification Process -- Using SCV for Verification -- Functional Verification Testplan -- Testbench Concepts using SystemC -- Verification Methodology.-Regression/Setup and Run -- Functional Coverage -- Dynamic Memory Modeling -- Post Synthesis Gate Simulation -- Appendices.
- 摘要: "As chip size and complexity continues to grow exponentially, the challenges of functional verification are becoming a critical issue in the electronics industry. It is now commonly heard that logical errors missed during functional verification are the most common cause of chip re-spins, and that the costs associated with functional verification are now outweighing the costs of chip design. To cope with these challenges engineers are increasingly relying on new design and verification methodologies and languages. Transaction-based design and verification, constrained random stimulus generation, functional coverage analysis, and assertion-based verification are all techniques that advanced design and verification teams routinely use today. Engineers are also increasingly turning to design and verification models based on C/C++ and SystemC in order to build more abstract, higher performance hardware and software models and to escape the limitations of RTL HDLs. This new book, Advanced Verification Techniques, provides specific guidance for these advanced verification techniques. The book includes realistic examples and shows how SystemC and SCV can be applied to a variety of advanced design and verification tasks."--Stuart Swan
- 電子資源: https://dbs.tnua.edu.tw/login?url=https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=114602
- 系統號: 005309590
- 資料類型: 電子書
- 讀者標籤: 需登入
- 引用網址: 複製連結
"As chip size and complexity continues to grow exponentially, the challenges of functional verification are becoming a critical issue in the electronics industry. It is now commonly heard that logical errors missed during functional verification are the most common cause of chip re-spins, and that the costs associated with functional verification are now outweighing the costs of chip design. To cope with these challenges engineers are increasingly relying on new design and verification methodologies and languages. Transaction-based design and verification, constrained random stimulus generation, functional coverage analysis, and assertion-based verification are all techniques that advanced design and verification teams routinely use today. Engineers are also increasingly turning to design and verification models based on C/C++ and SystemC in order to build more abstract, higher performance hardware and software models and to escape the limitations of RTL HDLs. This new book, Advanced Verification Techniques, provides specific guidance for these advanced verification techniques. The book includes realistic examples and shows how SystemC and SCV can be applied to a variety of advanced design and verification tasks." - Stuart Swan
來源: Google Book
來源: Google Book
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