Static crosstalk-noise analysis :for deep sub-micron digital designs
- 作者: Chen, Pinhong.
- 其他作者: Kirkpatrick, Desmond A. , Keutzer, Kurt.
- 出版: Norwell, MA : Kluwer Academic Publishers ©2004.
- 稽核項: 1 online resource (xviii, 113 pages) :illustrations.
- 標題: Crosstalk. , Machine Theory. , Computer Engineering. , COMPUTERS , Metal oxide semiconductors, Complementary. , Diaphonie. , HardwareGeneral. , COMPUTERS Machine Theory. , COMPUTERS Computer Engineering. , Bruit électronique. , COMPUTERS Hardware -- General. , MOS complémentaires. , Electronic books. , Electronic noise.
- ISBN: 1402080921 , 9781402080920
- 試查全文@TNUA:
- 附註: Includes bibliographical references. Introduction -- Miller Factor Computation for Coupling Delay -- Convergence of Switching Window Computation -- Speeding-Up Switching Window Computation -- Refinement of Switching Windows -- Functional Crosstalk Analysis -- Conclusions.
- 摘要: As the feature size decreases in deep sub-micron designs, coupling capacitance becomes the dominant factor in total capacitance. The resulting crosstalk noise may be responsible for signal integrity issues and significant timing variation. Traditionally, static timing analysis tools have ignored cross coupling effects between wires altogether. Newer tools simply approximate the coupling capacitance by a 2X Miller factor in order to compute the worst case delay. The latter approach not only reduces delay calculation accuracy, but can also be shown to underestimate the delay in certain scenarios. This book describes accurate but conservative methods for computing delay variation due to coupling. Furthermore, most of these methods are computationally efficient enough to be employed in a static timing analysis tool for complex integrated digital circuits. To achieve accuracy, a more accurate computation of the Miller factor is derived. To achieve both computational efficiency and accuracy, a variety of mechanisms for pruning the search space are detailed, including: -Spatial pruning - reducing aggressors to those in physical proximity, -Electrical pruning - reducing aggressors by electrical strength, -Temporal pruning - reducing aggressors using timing windows, -Functional pruning - reducing aggressors by Boolean functional analysis.
- 電子資源: https://dbs.tnua.edu.tw/login?url=https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=114607
- 系統號: 005309601
- 資料類型: 電子書
- 讀者標籤: 需登入
- 引用網址: 複製連結
As the feature size decreases in deep sub-micron designs, coupling capacitance becomes the dominant factor in total capacitance. The resulting crosstalk noise may be responsible for signal integrity issues and significant timing variation. Traditionally, static timing analysis tools have ignored cross coupling effects between wires altogether. Newer tools simply approximate the coupling capacitance by a 2X Miller factor in order to compute the worst case delay. The latter approach not only reduces delay calculation accuracy, but can also be shown to underestimate the delay in certain scenarios. This book describes accurate but conservative methods for computing delay variation due to coupling. Furthermore, most of these methods are computationally efficient enough to be employed in a static timing analysis tool for complex integrated digital circuits. To achieve accuracy, a more accurate computation of the Miller factor is derived. To achieve both computational efficiency and accuracy, a variety of mechanisms for pruning the search space are detailed, including: -Spatial pruning - reducing aggressors to those in physical proximity, -Electrical pruning - reducing aggressors by electrical strength, -Temporal pruning - reducing aggressors using timing windows, -Functional pruning - reducing aggressors by Boolean functional analysis.
來源: Google Book
來源: Google Book
評分