ASIC and FPGA verification :a guide to component modeling
- 作者: Munden, Richard.
- 出版: San Francisco, Calif. : Morgan Kaufmann ©2005.
- 稽核項: 1 online resource (1 volume).
- 叢書名: Morgan Kaufmann series in systems on silicon
- 標題: Field programmable gate arrays. , TECHNOLOGY & ENGINEERING , Réseaux logiques programmables par l'utilisateur. , TECHNOLOGY & ENGINEERING Electronics -- Circuits -- VLSI & ULSI. , TECHNOLOGY & ENGINEERING Electronics -- Circuits -- Logic. , Circuits intégrés à la demande. , ElectronicsCircuitsVLSI & ULSI. , COMPUTERS , Application specific integrated circuits. , COMPUTERS Logic Design. , Application-specific integrated circuits. , ElectronicsCircuitsLogic. , Logic Design. , Electronic books.
- ISBN: 0080475922 , 9780080475929
- 試查全文@TNUA:
- 附註: Includes index. 1. Introduction to Board-Level Verification; 2. Tour of a simple model; 3. VHDL packages for component models; 4. Introduction to SDF; 5. Anatomy of a VITAL Model; 6. Modeling Delays; 7. VITAL truth tables; 8. Modeling timing constraints; 9. Modeling registered devices; 10. Conditional delays and timing constraints; 11. Negative timing constraints; 12. Timing Files and Backannotation; 13. Adding Timing to Your RTL Code; 14. Modeling Memories; 15. Considerations for Component Modeling; 16. Modeling Component Centric Features; 17. Testbenches for Component Models.
- 摘要: Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of todays digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs. *Provides numerous models and a clearly defined methodology for performing board-level simulation. *Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification.
- 電子資源: https://dbs.tnua.edu.tw/login?url=https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=117163
- 系統號: 005311645
- 資料類型: 電子書
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- 引用網址: 複製連結
Richard Munden demonstrates how to create and use simulation models for verifying ASIC and FPGA designs and board-level designs that use off-the-shelf digital components. Based on the VHDL/VITAL standard, these models include timing constraints and propagation delays that are required for accurate verification of today's digital designs. ASIC and FPGA Verification: A Guide to Component Modeling expertly illustrates how ASICs and FPGAs can be verified in the larger context of a board or a system. It is a valuable resource for any designer who simulates multi-chip digital designs.*Provides numerous models and a clearly defined methodology for performing board-level simulation.*Covers the details of modeling for verification of both logic and timing. *First book to collect and teach techniques for using VHDL to model "off-the-shelf" or "IP" digital components for use in FPGA and board-level design verification.
來源: Google Book
來源: Google Book
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