附註:Includes bibliographical references and author index.
Side Channels I -- Towards Efficient Second-Order Power Analysis -- Correlation Power Analysis with a Leakage Model -- Power Analysis of an FPGA -- Modular Multiplication -- Long Modular Multiplication for Cryptographic Applications -- Leak Resistant Arithmetic -- Efficient Linear Array for Multiplication in GF(2 m) Using a Normal Basis for Elliptic Curve Cryptography -- Low Resources I -- Low-Power Elliptic Curve Cryptography Using Scaled Modular Arithmetic -- A Low-Cost ECC Coprocessor for Smartcards -- Comparing Elliptic Curve Cryptography and RSA on 8-bit CPUs -- Implementation Aspects -- Instruction Set Extensions for Fast Arithmetic in Finite Fields GF(p) and GF(2 m) -- Aspects of Hyperelliptic Curves over Large Prime Fields in Software Implementations -- Collision Attacks -- A Collision-Attack on AES -- Enhancing Collision Attacks -- Side Channels II -- Simple Power Analysis of Unified Code for ECC Double and Add -- DPA on n-Bit Sized Boolean and Arithmetic Operations and Its Application to IDEA, RC6, and the HMAC-Construction -- Side-Channel Attacks in ECC: A General Technique for Varying the Parametrization of the Elliptic Curve -- Switching Blindings with a View Towards IDEA -- Fault Attacks -- Fault Analysis of Stream Ciphers -- A Differential Fault Attack Against Early Rounds of (Triple- )DES -- Hardware Implementation I -- An Offset-Compensated Oscillator-Based Random Bit Source for Security Applications -- Improving the Security of Dual-Rail Circuits -- Side Channels III -- A New Attack with Side Channel Leakage During Exponent Recoding Computations -- Defeating Countermeasures Based on Randomized BSD Representations -- Pipelined Computation of Scalar Multiplication in Elliptic Curve Cryptosystems -- Efficient Countermeasures against RPA, DPA, and SPA -- Low Resources II -- Strong Authentication for RFID Systems Using the AES Algorithm -- TTS: High-Speed Signatures on a Low-Cost Smart Card -- Hardware Implementation II -- XTR Implementation on Recon
摘要:This book constitutes the refereed proceedings of the 6th International workshop on Cryptographic Hardware and Embedded Systems, CHES 2004, held in Cambridge, MA, USA in August 2004. The 32 revised full papers presented were carefully reviewed and selected from 125 submissions. The papers are organized in topical sections on side channels, modular multiplication, low resources, implementation aspects, collision attacks, fault attacks, hardware implementation, and authentication and signatures.
