Power-constrained testing of VLSI circuits

• 作者: Nicolici, Nicola.
• 其他作者: Al-Hashimi, Bashir.
• 出版: Boston : Kluwer Academic Publishers ©2003.
• 稽核項: 1 online resource (xi, 178 pages) :illustrations.
• 叢書名: Frontiers in electronic testing ;22
• 標題: TECHNOLOGY & ENGINEERING , Integrated circuits Very large scale integration -- Testing. , TECHNOLOGY & ENGINEERING Electronics -- Circuits -- VLSI & ULSI. , TECHNOLOGY & ENGINEERING Electronics -- Circuits -- Logic. , Integrated circuits Very large scale integration -- Protection. , Very large scale integrationTesting. , Thermal properties. , Semiconductors , COMPUTERS , COMPUTERS Logic Design. , Electronic books. , Semiconductors Thermal properties. , ElectronicsCircuitsVLSI & ULSI. , ElectronicsCircuitsLogic. , Very large scale integrationProtection. , Logic Design. , Integrated circuits
• ISBN: 0306487314 , 9780306487316
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• 附註: Includes bibliographical references (pages 163-173) and index. 1. Design and Test of Digital Integrated Circuits -- 2. Power Dissipation During Test -- 3. Approaches to Handle Test Power -- 4. Best Primary Input Change Time -- 5. Multiple Scan Chains -- 6. Power-Conscious Test Synthesis and Scheduling -- 7. Power Profile Manipulation -- 8. Conclusion.
• 摘要: Minimization of power dissipation in very large scale integrated (VLSI) circuits is important to improve reliability and reduce packaging costs. While many techniques have investigated power minimization during the functional (normal) mode of operation, it is important to examine the power dissipation during the test circuit activity is substantially higher during test than during functional operation. For example, during the execution of built-in self-test (BIST) in-field sessions, excessive power dissipation can decrease the reliability of the circuit under test due to higher temperature and current density. Power-Constrained Testing of VLSI Circuits focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. The first part of this book surveys the existing techniques for power constrained testing of VLSI circuits. In the second part, several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths are presented.
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