CMOS fractional-N synthesizers :design for high spectral purity and monolithic integration
- 作者: Muer, Bram de.
- 其他作者: Steyaert, Michiel,
- 出版: Boston : Kluwer Academic Publishers 2003.
- 稽核項: 1 online resource (xvii, 243 pages) :illustrations.
- 叢書名: The Kluwer international series in engineering and computer science ;724
- 標題: Frequency synthesizers. , TECHNOLOGY & ENGINEERING , TECHNOLOGY & ENGINEERING Electronics -- Circuits -- General. , TECHNOLOGY & ENGINEERING Electronics -- Circuits -- Integrated. , Metal oxide semiconductors, Complementary. , Very large scale integration. , Andre fag (naturvidenskab og teknik) Andre fag. , ElectronicsCircuitsIntegrated. , ElectronicsCircuitsGeneral. , Electronic books. , Integrated circuits Very large scale integration. , Integrated circuits
- ISBN: 0306480018 , 9780306480010
- ISBN: 1402073879 , 9781402073878
- 試查全文@TNUA:
- 附註: Includes bibliographical references (pages 243-256 and index. From the contents: Abstract -- List of Symbols and Abbreviations -- 1: Introduction -- 2: On Frequency Synthesis -- 3: High-Speed CMOS Prescalers -- 4: Monolithic CMOS LC-VCOs -- 5: Monolithic Phase Loops -- 6: A 1.8 GHz CMOS & Dgr; & Sgr; Fractional-N Frequency Synthesizer -- 7: Conclusions -- Index -- Bibliography.
- 摘要: CMOS Fractional-N Synthesizers starts with a comprehensive introduction to general frequency synthesis. Different architectures and synthesizer building blocks are discussed with their relative importance on synthesizer specifications. The process of synthesizer specification derivation is illustrated with the DCS-1800 standard as a general test case. The book tackles the design of fractional-N synthesizers in CMOS on circuit level as well as system level. The circuit level focuses on high-speed prescaler design up to 12 GHz in CMOS and on fully integrated, low-phase-noise LC-VCO design. High-Q inductor integration and simulation in CMOS is elaborated and flicker noise minimization techniques are presented, ranging from bias point choice to noise filtering techniques. On a higher level, a systematic design strategy has been developed that trades off all noise contributions and fast dynamics for integrated capacitance (area). Moreover, a theoretical DeltaSigma phase noise analysis is presented, extended with a fast non-linear analysis method to accurately predict the influence of PLL non-linearities on the spectral purity of the DeltaSigma fractional-N frequency synthesizers.
- 電子資源: https://dbs.tnua.edu.tw/login?url=https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=99308
- 系統號: 005320513
- 資料類型: 電子書
- 讀者標籤: 需登入
- 引用網址: 複製連結
CMOS Fractional-N Synthesizers starts with a comprehensive introduction to general frequency synthesis. Different architectures and synthesizer building blocks are discussed with their relative importance on synthesizer specifications. The process of synthesizer specification derivation is illustrated with the DCS-1800 standard as a general test case. The book tackles the design of fractional-N synthesizers in CMOS on circuit level as well as system level. The circuit level focuses on high-speed prescaler design up to 12 GHz in CMOS and on fully integrated, low-phase-noise LC-VCO design. High-Q inductor integration and simulation in CMOS is elaborated and flicker noise minimization techniques are presented, ranging from bias point choice to noise filtering techniques. On a higher level, a systematic design strategy has been developed that trades off all noise contributions and fast dynamics for integrated capacitance (area). Moreover, a theoretical DeltaSigma phase noise analysis is presented, extended with a fast non-linear analysis method to accurately predict the influence of PLL non-linearities on the spectral purity of the DeltaSigma fractional-N frequency synthesizers.
來源: Google Book
來源: Google Book
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