附註:Includes bibliographical references (page 457) and index.
Cover -- Title -- Table of Content -- 1. INTRODUCTION TO VERILOG HDL -- 1.1 Language Motivation -- 1.2 Tutorial Via Examples -- 1.3 Overview of Verilog HDL -- 1.4 Syntax Conventions -- 1.5 Exercises -- 2. DATA TYPES IN VERILOG -- 2.1 Overview -- 2.2 Value Systems -- 2.3 Data Declarations -- 2.4 Reg Declaration -- 2.5 Net Declaration -- 2.6 Port Types -- 2.7 Aggregates ... 1 and 2 Dimensional Arrays (Vectors and Memories) -- 2.8 Delays on Nets -- 2.9 Integer and Time -- 2.10 Real Declaration -- 2.11 Event Declaration -- 2.12 Parameter Declarations -- 2.13 Examples -- 2.14 Syntax -- 2.15 Hierarchical Names -- 2.16 Exercises -- 3. ABSTRACTION LEVELS IN VERILOG: BEHAVIORAL, RTL, AND STRUCTURAL -- 3.1 OVERVIEW -- 3.2 Behavioral Abstractions In Verilog -- 3.3 Register Transfer Level Abstractions in Verilog -- 3.4 Expressions -- 3.5 Operators in Expressions -- 3.6 Operands in Expressions -- 3.7 Special Considerations in Expressions -- 3.8 Syntax for Expressions -- 3.9 Example of Register Transfer Level of Abstraction -- 3.10 Structural Descriptions In Verilog -- 3.11 Exercises -- 4. SEMANTIC MODEL FOR VERILOG HDL -- 4.1 Introduction -- 4.2 Example -- 4.3 Simulation with Full Analysis -- 4.4 Log of a Typical Simulator -- 4.5 Log of an Ideal Simulator -- 4.6 Analysis and Concepts in Event-Driven Simulation in Verilog -- 4.7 Internal Data Structure Representation -- 4.8 Update and Evaluate Events -- 4.9 Order of Execution of Events in Verilog -- 4.10 Algorithm for Event-Driven Model for Verilog HDL -- 4.11 Highlights of the Algorithm ... Concurrent Processes and Event Cancelations -- 4.12 Exercises -- 5. BEHAVIORAL MODELING -- 5.1 Overview of Behavioral Modeling -- 5.2 Procedural Assignments -- 5.3 Conditional Statement -- 5.4 Case Statement -- 5.5 Loops -- 5.6 Begin-End Blocks -- 5.7 Wait Statements -- 5.8 Event and Delay Controls -- 5.9 Fork-Join Blocks -- 5.10 Functions and Tasks -- 5.11 Task Disabling -- 5.12 Assign-Deassign Statements -- 5.13 Force-Release Statements
摘要:The Verilog hardware description language (HDL) provides the ability to describe digital and analog systems. This ability spans the range from descriptions that express conceptual and architectural design to detailed descriptions of implementations in gates and transistors. Verilog was developed originally at Gateway Design Automation Corporation during the mid-eighties. Tools to verify designs expressed in Verilog were implemented at the same time and marketed. Now Verilog is an open standard of IEEE with the number 1364. Verilog HDL is now used universally for digital designs in ASIC, FPGA, microprocessor, DSP and many other kinds of design-centers and is supported by most of the EDA companies. The research and education that is conducted in many universities is also using Verilog. This book introduces the Verilog hardware description language and describes it in a comprehensive manner. Verilog HDL was originally developed and specified with the intent of use with a simulator. Semantics of the language had not been fully described until now. In this book, each feature of the language is described using semantic introduction, syntax and examples. Chapter 4 leads to the full semantics of the language by providing definitions of terms, and explaining data structures and algorithms. The book is written with the approach that Verilog is not only a simulation or synthesis language, or a formal method of describing design, but a complete language addressing all of these aspects. This book covers many aspects of Verilog HDL that are essential parts of any design process.
