附註:Includes bibliographical references and index.
Basics of circuit analysis -- Model-order reduction -- Generalized Y-delta transformation : fundamental theory -- Generalized Y-delta transformation : advance topics -- Y-delta transformation : application I : model stabilization -- Y-delta transformation : application II : realizable parasitic reduction -- Topological analysis of passive networks -- Exact symbolic analysis using determinant decision diagrams -- S-expanded determinant decision diagrams for symbolic analysis -- DDD based approximation for analog behavioral modeling -- Hierarchical symbolic analysis and hierarchical model order reduction.
摘要:The IC industry, including digital and analog circuit design houses, electrical design automation software vendors, library and IP providers, and foundries all face grand challenges in designing nanometer VLSI systems. The design productivity gap between nanometer VLSI technologies and today's design capabilities mainly comes from the exponentially growing complexity of VLSI systems due to relentless pushing for integration. The physical effects on the performance and reliability of these systems are becoming more pronounced. Efficient modeling and reduction of both the passive and active circuits is essential for hierarchical and IP-based reuse design paradigms. Symbolic Analysis and Reducation of VLSI Circuits presents the symbolic approach to the modeling and reduction of both the passive parasitic linear networks and active analog circuits. It reviews classic symbolic analysis methods and presents state-of-art developments for interconnect reduction and the behavioral modeling of active analog circuits. The text includes the most updated discoveries such as Y-Delta transformation and DDD-graph symbolic representation which allow analysis and modeling of much larger circuitry than ever before.
