附註:Includes bibliographical references and index.
Power considerations in sub-micron digital CMOS -- Power considerations in sub-micron analog CMOS -- Gm-C integrators for low-power and low voltage applications. A gaussian polyphase filter for mobile transceivers in 0.35?m CMOS -- Chopping: a technique for noise and offset reduction -- Low-noise, low residual offset, chopped amplifiers for high-end applications -- A 16-bit D/A interface with Sinc approximated semidigital reconstruction filter -- Conclusions.
摘要:The work presented in Power Trade-offs and Low Power in Analog CMOS ICs concerns power, noise and accuracy in CMOS Analog IC Design. In the presented material it is shown that power, noise and accuracy should be treated in an unitary way, the three terms being well inter-related. The book is divided in a theoretical part which covers sub-micron digital and sub-micron analog followed by an applicative part where accuracy related power and noise related power is encountered. The main part of the book deals with analog circuits working in a digital environment where the process has been optimized for digital applications.
