Networks on chip
- 其他作者: Jantsch, Axel. , Tenhunen, Hannu.
- 出版: Boston : Kluwer Academic Publishers ©2003.
- 稽核項: 1 online resource (viii, 303 pages) :illustrations.
- 標題: COMPUTERS Networking -- Vendor Specific. , COMPUTERS , NetworkingVendor Specific. , Systems on a chip , Computer networks. , Data Transmission SystemsGeneral. , Systems on a chip Design and construction. , Electronic books. , COMPUTERS Data Transmission Systems -- General. , Design and construction.
- ISBN: 1402073925 , 9781402073922
- ISBN: 1402073925
- 試查全文@TNUA:
- 附註: Includes bibliographical references. From the contents: Preface -- Part I: System Design and Methodology -- Part II: Hardware and Basic Infrastructure -- Part III: Software and Application Interfaces.
- 摘要: As the number of processor cores and IP blocks integrated on a single chip is steadily growing, a systematic approach to design the communication infrastructure becomes necessary. Different variants of packed switched on-chip networks have been proposed by several groups during the past two years. This book summarizes the state of the art of these efforts and discusses the major issues from the physical integration to architecture to operating systems and application interfaces. It also provides a guideline and vision about the direction this field is moving to. Moreover, the book outlines the consequences of adopting design platforms based on packet switched network. The consequences may in fact be far reaching because many of the topics of distributed systems, distributed real-time systems, fault tolerant systems, parallel computer architecture, parallel programming as well as traditional system-on-chip issues will appear relevant but within the constraints of a single chip VLSI implementation.
- 電子資源: https://dbs.tnua.edu.tw/login?url=https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=117809
- 系統號: 005321518
- 資料類型: 電子書
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- 引用網址: 複製連結
As the number of processor cores and IP blocks integrated on a single chip is steadily growing, a systematic approach to design the communication infrastructure becomes necessary. Different variants of packed switched on-chip networks have been proposed by several groups during the past two years. This book summarizes the state of the art of these efforts and discusses the major issues from the physical integration to architecture to operating systems and application interfaces. It also provides a guideline and vision about the direction this field is moving to. Moreover, the book outlines the consequences of adopting design platforms based on packet switched network. The consequences may in fact be far reaching because many of the topics of distributed systems, distributed real-time systems, fault tolerant systems, parallel computer architecture, parallel programming as well as traditional system-on-chip issues will appear relevant but within the constraints of a single chip VLSI implementation.
來源: Google Book
來源: Google Book
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