Verification by error modeling :using testing techniques in hardware verification
- 作者: Radecka, Katarzyna.
- 其他作者: Zilic, Zeljko.
- 出版: Boston : Kluwer Academic Publishers 2003.
- 稽核項: 1 online resource (xiv, 216 pages) :illustrations.
- 叢書名: Frontiers in electronic testing ;25
- 標題: TECHNOLOGY & ENGINEERING , TECHNOLOGY & ENGINEERING Electronics -- Circuits -- VLSI & ULSI. , COMPUTERS , TECHNOLOGY & ENGINEERING Electronics -- Circuits -- Logic. , Very large scale integrationComputer-aided design. , Verification. , ElectronicsCircuitsVLSI & ULSI. , Error analysis (Mathematics) , COMPUTERS Logic Design. , Integrated circuits Verification. , Electronic books. , Logic Design. , ElectronicsCircuitsLogic. , Integrated circuits Very large scale integration -- Computer-aided design. , Integrated circuits
- ISBN: 1402076525 , 9781402076527
- ISBN: 1402076525
- 試查全文@TNUA:
- 附註: Includes bibliographical references and index.
- 電子資源: https://dbs.tnua.edu.tw/login?url=https://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&AN=118522
- 系統號: 005321605
- 資料類型: 電子書
- 讀者標籤: 需登入
- 引用網址: 複製連結
This book presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. It brings the results in the direction of merging manufacturing test vector generation and verification.
來源: Google Book
來源: Google Book
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