附註:Includes bibliographical references (pages 229-239) and index.
Sect. I. Design & Test of Memories -- Ch. 1. Opening Pandora's Box -- Ch. 2. Static Random Access Memories -- Ch. 3. Multi-Port Memories -- Ch. 4. Silicon On Insulator Memories -- Ch. 5. Content Addressable Memories -- Ch. 6. Dynamic Random Access Memories -- Ch. 7. Non-Volatile Memories -- Sect. II. Memory Testing -- Ch. 8. Memory Faults -- Ch. 9. Memory Patterns -- Sect. III. Memory Self Test -- Ch. 10. BIST Concepts -- Ch. 11. State Machine BIST -- Ch. 12. Micro-Code BIST -- Ch. 13. BIST and Redundancy -- Ch. 14. Design For Test and BIST -- Ch. 15. Conclusions -- App. A. Further Memory Fault Modeling -- App. B. Further Memory Test Patterns -- App. C. State Machine HDL.
摘要:"High Performance Memory Testing: Design Principles, Fault Modeling and Self-Test is Written for the professional and the researcher to help them understand the memories that are being tested."--Jacket.
