附註:Cover -- Table of Contents -- About the Cover -- Foreword -- Preface -- Why This Book Is Important -- What This Book Is About -- What Prior Knowledge You Should Have -- Reading Paths -- VHDL versus Verilog -- For More Information -- Acknowledgements -- Chapter 1 What is Verification? -- What is a Testbench? -- The Importance of Verification -- Reconvergence Model -- The Human Factor -- What Is Being Verified? -- Functional Verification Approaches -- Testing Versus Verification -- Verification and Design Reuse -- The Cost of Verification -- Summary -- Chapter 2 Verification Tools -- Linting Tools -- Simulators -- Third-Party Models -- Waveform Viewers -- Code Coverage -- Verification Languages -- Revision Control -- Issue Tracking -- Metrics -- Summary -- Chapter 3 The Verification Plan -- The Role of the Verification Plan -- Levels of Verification -- Verification Strategies -- From Specification to Features -- From Features to Testcases -- From Testcases to Testbenches -- Summary -- Chapter 4 Behavioral Hardware Description Languages -- Behavioral versus RTL Thinking -- You Gotta Have Style! -- Structure of Behavioral Code -- Data Abstraction -- The HDL Parallel Engine -- Verilog Portability Issues -- Summary -- Chapter 5 Stimulus and Response -- Simple Stimulus -- Verifying the Output -- Self-Checking Testbenches -- Complex Stimulus -- Complex Response -- Predicting the Output -- Summary -- Chapter 6 Architecting Testbenches -- Reusable Verification Components -- Verilog Implementation -- VHDL Implementation -- Autonomous Generation and Monitoring -- Input and Output Paths -- Verifying Configurable Designs -- Summary -- Chapter 7 Simulation Management -- Behavioral Models -- Pass or Fail? -- Managing Simulations -- Regression -- Summary -- Appendix A Coding Guidelines -- Directory Structure -- General Coding Guidelines -- Naming Guidelines -- HDL Coding Guidelines -- Afterwords
摘要:Writing Testbenches: Functional Verification of HDL Models first introduces the necessary concepts and tools of verification, then describes a process for carrying out an effective functional verification of a design. This book also presents techniques for applying a stimulus and monitoring the response of a design by abstracting the operations using bus-functional models. The architecture of testbenches built around these bus-functional models is important for minimizing development and maintenance effort. Behavioral modeling is another important concept presented in this book. It is used to parallelize the implementation and verification of a design and to perform more efficient simulations. For many, behavioral modeling is synonymous with synthesizeable or RTL modeling. In this book, the term `behavioural' is used to describe any model that adequately emulates the functionality of a design, usually using non-synthesizeable constructs and coding style. Writing Testbenches: Functional Verification of HDL Models focuses on the functional verification of hardware designs using either VHDL or Verilog. The reader should have at least a basic knowledge of one of the languages. Ideally, he or she should have experience in writing synthesizeable models and be familiar with running a simulation using any of the available VHDL or Verilog simulators. From the Foreword `With gate counts and system complexity growing exponentially, engineers confront the most perplexing challenge in product design: functional verification. The bulk of the time consumed in the design of new ICs and systems is now spent on verification. New and interesting design technologies like physical synthesis and design reuse that create ever- larger designs only aggravate the problem. What the EDA tool industry has continuously failed to realize is that the real problem is not how to create a 12 million gate IC that runs at 600 MHz, but how to verify it. This text marks the first genuine effort at def
