Circuit techniques for low-voltage and high-speed A/D converters

• 作者: Waltari, Mikko E.
• 其他作者: Halonen, K. A. I.
• 出版: Boston : Kluwer Academic Publishers ©2002.
• 稽核項: 1 online resource (vii, 254 pages) :illustrations.
• 叢書名: Kluwer international series in engineering and computer science ;SECS 709.Analog circuits and signal processing
• 標題: Low voltage systems. , Analog-to-digital converters. , Convertisseurs analogique-numérique. , COMPUTERS , Circuits électroniques. , Data Transmission SystemsGeneral. , Electronic books. , Electronic circuits. , COMPUTERS Data Transmission Systems -- General. , Basse tension.
• ISBN: 1402072449 , 9781402072444
• ISBN: 1402072449
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• 附註: Includes bibliographical references and index.
• 摘要: The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage. Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented. It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes. An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock
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